1. Technical Field
The present invention relates to a method and apparatus for data processing in general, and in particular to a method and apparatus for processing instructions within a processor. Still more particularly, the present invention relates to a method and apparatus for performing ADD and ROTATE as a single instruction within a processor.
2. Description of the Prior Art
An addition operation forms the basis for many other processing operations within a processor, from counting to multiplying to filtering. As a result, from a processor design standpoint, there is a tremendous incentive to improve the speed of any adder circuit that perform addition operations by which two binary numbers are added together.
Accordingly, a significant amount of silicon area is devoted in most general purpose processors for the execution of fixed point and/or integer ADD instructions such that each of these ADD instructions can be completed within a single processor cycle. Occasionally, a separate macro may even be dedicated to execute these ADD instructions, with the macro design optimized for addition operations. A macro is defined as a collection of circuits designed to perform an operation on multiple inputs to produce an output.
Under the prior art, an ADD instruction followed by a ROTATE instruction for the sum from the ADD instruction requires at least two processor cycles to complete. In order to further improve the processor performance by staying true to the philosophy of improving the performance of added circuits within the processor as discussed above, it would be desirable to provide a method and apparatus for performing both ADD and ROTATE instructions as a single instruction. As such, both ADD and ROTATE instructions can be completed within a single processor cycle.